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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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P5021 데이터시트(PDF) 144 Page - NXP Semiconductors |
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P5021 데이터시트(HTML) 144 Page - NXP Semiconductors |
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144 / 155 page  P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Hardware design considerations Freescale Semiconductor 144 3.6.2 Aurora configuration signals Correct operation of the Aurora interface requires configuration of a group of system control pins as demonstrated in Figure 57 and Figure 58. Care must be taken to ensure that these pins are maintained at a valid negated state under normal operating conditions as most have asynchronous behavior and spurious assertion gives unpredictable results. Freescale recommends that the Aurora 22 pin duplex connector be designed into the system as shown in Figure 59 or the 70 pin duplex connector be designed into the system as shown in Figure 60. If the Aurora interface is not used, Freescale recommends the legacy COP header be designed into the system as described in Section 3.6.1.1, “Termination of unused signals.” Figure 57. Aurora 22 pin connector duplex pinout 3 13 9 5 1 6 10 15 11 7 16 12 8 4 1 2 TX0+ TX0- GND VIO (VSense) TCK TMS TDI TDO TRST Vendor I/O 1 TX1+ TX1- GND RX0+ RX0- 17 18 20 19 21 22 GND RX1+ RX1- Vendor I/O 0 14 Vendor I/O 3 Vendor I/O 2 RESET |
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