MPC8308CVMADDA datasheet(59/95 Pages) NXP

59 / 95 page

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

Package and Pin Listings

This figure shows the SPI timing in slave mode (external clock).

Figure 50. SPI AC Timing in Slave Mode (External Clock) Diagram

This figure shows the SPI timing in master mode (internal clock).

Figure 51. SPI AC Timing in Master Mode (Internal Clock) Diagram

20 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions. The MPC8308 is available in

a moulded array process ball grid array (MAPBGA). For information on the MAPBGA, see Section 20.1,

“Package Parameters for the MPC8308 MAPBGA,” and Section 20.2, “Mechanical Dimensions of the

MPC8308 MAPBGA.”

20.1

Package Parameters for the MPC8308 MAPBGA

The package parameters are as provided in the following list. The package type is 19 mm

 19 mm, 473

MAPBGA.

Package outline

19 mm

19 mm

Interconnects

473

Pitch

0.80 mm

Module height (typical)

1.39 mm

Solder Balls

96.5 Sn/ 3.5Ag

Ball diameter (typical)

0.40 mm

SPICLK (input)

tNEIXKH

tNEIVKH

tNEKHOV

Input Signals:

SPIMOSI

(See Note)

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

SPICLK (output)

tNIIXKH

tNIKHOV

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

tNIIVKH

MPC8308CVMADDA 데이터시트(PDF) 59 Page - NXP Semiconductors

MPC8308CVMADDA 데이터시트(HTML) 59 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

데이터시트 다운로드

링크 URL