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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MPC8308CVMADDA 데이터시트(PDF) 12 Page - NXP Semiconductors |
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MPC8308CVMADDA 데이터시트(HTML) 12 Page - NXP Semiconductors |
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12 / 95 page  MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4 12 Freescale Semiconductor DDR2 SDRAM This figure illustrates the DDR2 input timing diagram showing the tDISKEW timing parameter. Figure 4. Timing Diagram for tDISKEW 6.2.2 DDR2 SDRAM output AC timing specifications Table 18. DDR2 SDRAM Output AC Timing Specifications Parameter Symbol 1 Min Max Unit Notes MCK[n] cycle time, MCK[n]/MCK[n] crossing tMCK 7.5 10 ns 2 ADDR/CMD output setup with respect to MCK 266 MHz tDDKHAS 2.9 — ns 3 ADDR/CMD output hold with respect to MCK 266 MHz tDDKHAX 2.33 — ns 3 MCS[n] output setup with respect to MCK 266 MHz tDDKHCS 2.5 — ns 3 MCS[n] output hold with respect to MCK 266 MHz tDDKHCX 3.15 — ns 3 MCK to MDQS Skew tDDKHMH –0.6 0.6 ns 4 MDQ//MDM/MECC output setup with respect to MDQS 266 MHz tDDKHDS, tDDKLDS 900 — ps 5 MDQ//MDM/MECC output hold with respect to MDQS 266 MHz tDDKHDX, tDDKLDX 1100 — ps 5 MCK[n] MCK[n] tMCK MDQ[x]/ MDQS[n] tDISKEW D1 D0 tDISKEW MECC[x] |
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