IMX8MPCEC datasheet(44/111 Pages) NXP

44 / 111 page

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Electrical characteristics

3.7.1

Reset timings parameters

Figure 11 shows the reset timing and Table 33 lists the timing parameters.

Figure 11. Reset timing diagram

3.7.2

WDOG Reset timing parameters

Figure 12 shows the WDOG reset timing and Table 34 lists the timing parameters.

Figure 12. WDOGx_B timing diagram

NOTE

RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or

approximately 30 µs.

NOTE

WDOGx_B output signals (for each one of the Watchdog modules) do not

have dedicated pins, but are muxed out through the IOMUX. See the

IOMUXC chapter of the i.MX 8M Plus Applications Processor Reference

Manual (IMX8MPRM) for detailed information.

3.7.3

DDR SDRAM–specific parameters (LPDDR4 and DDR4)

The i.MX 8M Plus Family of processors have been designed and tested to work with JEDEC

JESD209-4A–compliant LPDDR4 memory and JESD79-4A compliant DDR4 memory. Timing diagrams

Table 33. Reset timing parameters

Parameter

Min Max

Unit

CC1

Duration of POR_B to be qualified as valid.

Note: POR_B rise/fall times must be 5 ns or less.

—

RTC_XTALI cycle

Table 34. WDOGx_B timing parameters

Parameter

Min

Max

Unit

CC3

Duration of WDOG1_B Assertion

—

RTC_XTALI cycle

POR_B

CC1

(Input)

WDOGx_B

CC3

(Output)

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