IMX8MPCEC datasheet(72/111 Pages) NXP

72 / 111 page

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Electrical characteristics

3.8.10 PCIe 3.0 PHY parameters

The PCIe interface is designed to be compatible with PCIe specification Gen3 x1 lane and supports the

PCI Express 1.1/2.0/3.0 standards.

3.8.10.1 PCIe DC parameters

The DC parameters of PCIe are compliant with PCI Express Base Specification, rev3.0.

3.8.10.2 PCIE_RESREF reference resistor connection

The external resistor-referred current is generated by using 8.2 k

 1% precision resistor, which is

connected between the PCIE_RESREF pad and ground outside the chip.

3.8.11

Pulse width modulator (PWM) timing parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

Figure 39 depicts the timing of the PWM, and Table 55 lists the PWM timing parameters.

Figure 39. PWM timing

Skew calibration

Tskewcal

(Initial)

Timing that the

transmitter drives

the skew calibration

pattern in the initial

skew calibration

mode

—

100

µs

—2^15

—

Tskewcal

(Periodic)

Timing that the

transmitter drives

the skew calibration

pattern in the

periodic skew

calibration mode

——

—

µs

—2^13

—

Table 54. DC power supply, LP-RX, and skew calibration specifications (continued) (Sheet 2 of 2)

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