IMX8MPCEC datasheet(79/111 Pages) NXP

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Electrical characteristics

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Figure 47. SAI timing—Master modes

SAI_BCLK to SAI_FS output invalid

—

SAI_BCLK to SAI_TXD valid

—

SAI_BCLK to SAI_TXD invalid

—

SAI_RXD/SAI_FS input setup before SAI_BCLK

—

S10

SAI_RXD/SAI_FS input hold after SAI_BCLK

—

Table 67. Slave mode SAI timing (50 MHz)1

1 TX does not support 50 MHz operation in Slave mode.

Num

Characteristic

Min

Max

Unit

S11

SAI_BCLK cycle time (input)

—

S12

SAI_BCLK pulse width high/low (input)

40%

60%

BCLK period

S13

SAI_FS input setup before SAI_BCLK

—

S14

SAI_FA input hold after SAI_BCLK

—

S17

SAI_RXD setup before SAI_BCLK

—

S18

SAI_RXD hold after SAI_BCLK

—

Table 68. Slave mode SAI timing (25 MHz)

Num

Characteristic

Min

Max

Unit

S11

SAI_BCLK cycle time (input)

—

S12

SAI_BCLK pulse width high/low (input)

40%

60%

BCLK period

Table 66. Master mode SAI timing (25 MHz) (continued)

Num

Characteristic

Min

Max

Unit

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