IMX8MPCEC datasheet(51/111 Pages) NXP

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Electrical characteristics

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

3.8.2.4

HS200 Mode AC timing

Figure 18 depicts the timing of HS200 mode, and Table 42 lists the HS200 timing characteristics.

Figure 18. HS200 timing

iti

SD4

Output skew from data of edge of SCK

tOSkew1

0.45

—

SD5

Output skew from edge of SCk to data

tOSkew2

0.45

—

uSDHC Input/Card Outputs DAT (Reference to Strobe)

SD6

uSDHC input skew

tRQ

—0.45

SD7

uSDHC hold skew

tRQH

—0.45

Table 42. HS200 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency Period

tCLK

5.0

—

SD2

Clock Low Time

tCL

0.3 x tCLK

0.7 x tCLK

SD3

Clock High Time

tCH

0.3 x tCLK

0.7 x tCLK

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)

SD5

uSDHC Output Delay

tOD

-1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1

1 HS200 is for 8 bits while SDR104 is for 4 bits.

SD8

uSDHC Output Data Window

tODW

0.5 x tCLK

—ns

Table 41. HS400 interface timing specification (continued)

Parameter

Symbols

Min

Max

Unit

SCK

8-bit output from uSDHC to eMMC

8-bit input from eMMC to uSDHC

SD8

SD4/SD5

SD2

SD3

SD1

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