IMX8MPCEC datasheet(77/111 Pages) NXP

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Electrical characteristics

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Figure 45. FlexSPI output timing in SDR mode

3.8.12.2.2 DDR mode

TDSO

[D:] Output data setup time

—

TDHO

[D:] Output data hold time

—

TCSS

[D:] Chip select output setup time

3 x TCK - 1

—

TCSH

[D:] Chip select output hold time

3 x TCK - 1

—

1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. See the

FlexSPI SDR input timing specifications.

NOTE

TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the

default values are shown above. See the i.MX 8M Plus Applications

Processor Reference Manual (IMX8MPRM) for more details.

Table 64. FlexSPI output timing in DDR mode

Symbol

Parameter

Min.

Max.

Unit

—

[D:] Frequency of operation1

1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. See the

FlexSPI SDR input timing specifications.

NOTE

TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the

default values are shown above. See the i.MX 8M Plus Applications

Processor Reference Manual (IMX8MPRM) for more details.

—166

MHz

TCK

[D:] SCK clock period

6.02

—

TDSO

[D:] Output data setup time

—

0.6

TDHO

[D:] Output data hold time

0.6

—

TCSS

[D:] Chip select output setup time

3 x TCK - 1.075

—

TCSH

[D:] Chip select output hold time

3 x TCK - 1.075

—

Table 63. FlexSPI output timing in SDR mode (continued)

Symbol

Parameter

Min.

Max.

Unit

TCSS

TCK

TCSH

TDVO

TDHO

TDVO

TDHO

SCK

SIO[0:7]

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