IMX8MPCEC datasheet(67/111 Pages) NXP

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Electrical characteristics

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Figure 36. NAND_DQS/NAND_DQ read valid window

For DDR Source Synchronous mode, Figure 36 shows the timing diagram of

NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 0.85 ns (max) and 1 ns

(max) for tQHS at 200 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of an

delayed NAND_DQS signal, which can be provided by an internal DPLL. The delay value can be

controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI

chapter of the i.MX 8M Plus Applications Processor Reference Manual [IMX8MPRM]). Generally, the

typical delay value of this register is equal to 0x7 which means 1/4 clock cycle delay expected. But if the

board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the

board delay.

Table 51. Source Synchronous mode timing parameters1

1 GPMI’s Source Synchronous mode output timing can be controlled by the module’s internal registers

GPMI_TIMING2_CE_DELAY,GPMI_TIMING_PREAMBLE_DELAY,GPMI_TIMING2_POST_DELAY.ThisACtimingdepends

on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.

Parameter

Symbol

Timing

T = GPMI Clock Cycle

Unit

Min.

Max.

NF18 NAND_CE0_B access time

tCE

CE_DELAY

 T - 0.79 [see note2]

2 T = tCK(GPMI clock period) –0.075 ns (half of maximum p-p jitter).

NF19 NAND_CE0_B hold time

tCH

0.5

 tCK - 0.63 [see note2]ns

NF20 Command/address NAND_DATAxx setup time

tCAS

0.5

 tCK - 0.05

NF21 Command/address NAND_DATAxx hold time

tCAH

0.5

 tCK - 1.23

NF22 clock period

tCK

—

NF23 preamble delay

tPRE

PRE_DELAY

 T - 0.29 [see note2]ns

NF24 postamble delay

tPOST

POST_DELAY

 T - 0.78 [see note2]ns

NF25 NAND_CLE and NAND_ALE setup time

tCALS

0.5

 tCK - 0.86

NF26 NAND_CLE and NAND_ALE hold time

tCALH

0.5

 tCK - 0.37

NF27 NAND_CLK to first NAND_DQS latching transition

tDQSS

T - 0.41 [see note2]ns

NF28 Data write setup

—

0.25

 tCK - 0.35

NF29 Data write hold

—

0.25

 tCK - 0.85

NF30 NAND_DQS/NAND_DQ read setup skew

—

2.06

NF31 NAND_DQS/NAND_DQ read hold skew

—

1.95

NF30

NF31

NF30

NF31

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