IMX8MPCEC datasheet(46/111 Pages) NXP

46 / 111 page

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Electrical characteristics

3.8.1

ECSPI timing parameters

This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing

parameters for master and slave modes.

3.8.1.1

ECSPI Master mode timing

Figure 13 depicts the timing of ECSPI in master mode. Table 36 lists the ECSPI master mode timing

characteristics.

Figure 13. ECSPI Master mode timing diagram

Table 36. ECSPI Master mode timing parameters

Parameter

Symbol

Min

Max Unit

CS1

ECSPIx_SCLK Cycle Time–Read

ECSPIx_SCLK Cycle Time–Write

tclk

See Table 37

—ns

CS2

ECSPIx_SCLK High or Low Time–Read

ECSPIx_SCLK High or Low Time–Write

tSW

21.5

—ns

CS3

ECSPIx_SCLK Rise or Fall1

1 See specific I/O AC parameters Section 3.5, I/O AC parameters.

tRISE/FALL

——

CS4

ECSPIx_SS_B pulse width

tCSLH

Half ECSPIx_SCLK period

—

CS5

ECSPIx_SS_B Lead Time (CS setup time)

tSCS

Half ECSPIx_SCLK period - 4

—

CS6

ECSPIx_SS_B Lag Time (CS hold time)

tHCS

Half ECSPIx_SCLK period - 2

—

CS7

ECSPIx_MOSI Propagation Delay (CLOAD =20pF)

tPDmosi

-1

CS8

ECSPIx_MISO Setup Time

tSmiso

1.23

—

CS9

ECSPIx_MISO Hold Time

tHmiso

3.09

—

CS10 RDY to ECSPIx_SS_B Time2

2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

tSDRY

5—

CS7

CS2

CS4

CS6

CS5

CS8

CS9

ECSPIx_SCLK

ECSPIx_SS_B

ECSPIx_MOSI

ECSPIx_MISO

ECSPIx_RDY_B

CS10

CS3

CS1

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