IMX8MPCEC datasheet(48/111 Pages) NXP

48 / 111 page

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Electrical characteristics

3.8.2

Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC

timing

This section describes the electrical information of the uSDHC, which includes SD/eMMC5.1 (single data

rate) timing, eMMC5.1/SD3.0 (dual data rate) timing and SDR50/SDR104 AC timing.

3.8.2.1

SD3.0/eMMC5.1 (single data rate) AC timing

Figure 15 depicts the timing of SD3.0/eMMC5.1, and Table 39 lists the SD3.0/eMMC5.1 timing

characteristics.

Figure 15. SD3.0/eMMC5.1 (SDR) timing

CS8 ECSPIx_MOSI Hold Time

tHmosi

4—

CS9 ECSPIx_MISO Propagation Delay (CLOAD =20pF)

tPDmiso

419

Table 39. SD3.0/eMMC5.1 (SDR) interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (Low Speed)

fPP

400

kHz

Clock Frequency (SD/SDIO Full Speed/High Speed)

fPP

25/50

MHz

Clock Frequency (MMC Full Speed/High Speed)

fPP

20/52

MHz

Clock Frequency (Identification Mode)

fOD

100

400

kHz

SD2

Clock Low Time

tWL

7—

SD3

Clock High Time

tWH

7—

Table 38. ECSPI Slave mode timing parameters (continued) (Sheet 2 of 2)

Parameter

Symbol

Min

Max

Unit

SD1

SD3

SD5

SD4

SD7

SDx_CLK

SD2

SD8

SD6

Output from uSDHC to card

Input from card to uSDHC

SDx_DATA[7:0]

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