LXT971ABC datasheet(28/90 Pages) INTEL

부품명	LXT971ABC

상세설명	3.3V Dual-Speed Fast Ethernet PHY Transceiver

PDF	90 Pages

Scroll/Zoom	100%

제조업체	INTEL [Intel Corporation]

홈페이지	http://www.intel.com

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28 / 90 page

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

3.4.3

Reduced Power Modes

The LXT971A offers two power-down modes and a sleep mode.

3.4.3.1

Hardware Power Down

The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High,

the following conditions are true:

• The LXT971A network port and clock are shut down.

• All outputs are three-stated.

• All weak pad pull-up and pull-down resistors are disabled.

• The MDIO registers are not accessible.

Figure 7. Initialization Sequence

MDDIS Voltage

Level?

High

Low

MDIO Control

Mode

Hardware Control

Mode

Disable MDIO Read and

Write Operations

Reset MDIO Registers to

values read at H/W

Control Interface at last

Hardware Reset

MDIO Controlled Operation

(MDIO Writes Enabled)

Power-up or Reset

Initialize MDIO Registers

Read H/W Control

Interface

Software

Reset?

Yes

LXT971ABC 데이터시트(PDF) 28 Page - Intel Corporation