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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LXT971ABC 데이터시트(PDF) 39 Page - Intel Corporation |
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LXT971ABC 데이터시트(HTML) 39 Page - Intel Corporation |
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39 / 90 page  LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet 39 Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 In the receive direction, the PCS layer performs the opposite function, substituting two preamble nibbles for the SSD. 3.7.3.1.2 Dribble Bits The LXT971A handles dribbles bits in all modes. If one to four dribble bits are received, the nibble is passed across the MII, and padded with ones if necessary. If five to seven dribble bits are received, the second nibble is not sent to the MII bus. Figure 20. Protocol Sublayers Encoder/Decoder Serializer/De-serializer Link/Carrier Detect PCS Sublayer PMA Sublayer MII Interface PECL Interface Fiber Transceiver LXT971A 100BASE-TX 100BASE-FX Scrambler/ De-scrambler PMD Sublayer |
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