LXT971ABC datasheet(43/90 Pages) INTEL

43 / 90 page

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

3.7.3.3.3 Programmable Slew Rate Control

The LXT971A device supports a slew rate mechanism whereby one of four pre-selected slew rates

can be used. This allows the designer to optimize the output waveform to match the characteristics

of the magnetics. The slew rate is determined by the TxSLEW pins as shown in Table 4 on

page 18.

3.7.3.4

Fiber PMD Sublayer

The LXT971A provides a Low Voltage PECL interface for connection to an external 3.3 V or 5.0 V

fiber-optic transceiver. (The external transceiver provides the PMD function for fiber media.) The

LXT971A uses an NRZI format for the fiber interface. The fiber interface operates at 100 Mbps

and does not support 10FL applications.

3.8

10 Mbps Operation

The LXT971A operates as a standard 10BASE-T transceiver. The LXT971A supports all the

standard 10 Mbps functions. During 10BASE-T operation, the LXT971A transmits and receives

Manchester-encoded data across the network link. When the MAC is not actively transmitting data,

the LXT971A drives link pulses onto the line.

In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded

signals received from the network are decoded by the LXT971A and sent across the MII to the

MAC.

The LXT971A does not support fiber connections at 10 Mbps.

3.8.1

10BASE-T Preamble Handling

The LXT971A offers two options for preamble handling, selected by Register bit 16.5. In

10BASE-T Mode when 16.5 = 0, the LXT971A strips the entire preamble off of received packets.

CRS is asserted coincident with SFD. RX_DV is held Low for the duration of the preamble. When

RX_DV is asserted, the very first two nibbles driven by the LXT971A are the SFD “5D” hex

followed by the body of the packet.

In 10BASE-T mode with 16.5 = 1, the LXT971A passes the preamble through the MII and asserts

RX_DV and CRS simultaneously. In 10BASE-T loopback, the LXT971A loops back whatever the

MAC transmits to it, including the preamble.

3.8.2

10BASE-T Carrier Sense

For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on

reception of an end-of-frame (EOF) marker. Register bit 16.7 allows CRS de-assertion to be

synchronized with RX_DV de-assertion. Refer to Table 52 on page 81.

3.8.3

10BASE-T Dribble Bits

The LXT971A device handles dribbles bits in all modes. If one to four dribble bits are received, the

nibble is passed across the MII, padded with ones if necessary. If five to seven dribble bits are

received, the second nibble is not sent to the MII bus.

LXT971ABC 데이터시트(PDF) 43 Page - Intel Corporation

LXT971ABC 데이터시트(HTML) 43 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

데이터시트 다운로드

링크 URL