UPD17062 datasheet(157/298 Pages) RENESAS

157 / 298 page

155

µPD17062

13.3

DEVICE OPERATION MODE SPECIFIED AT THE CE PIN

The CE pin controls the following items according to the level and positive-going edge of its input signal.

(1) Whether to enable or disable the clock stop instruction

(2) Whether to reset the device

Sections 13.3.1 and 13.3.2 explain the above items, respectively.

13.3.1

Controlling Whether to Enable or Disable the Clock Stop Instruction

The clock stop instruction, STOP s, is effective only when the CE pin is at a low level.

If the STOP s instruction is executed when the CE pin is at a high level, it is treated as a no-operation (NOP)

instruction.

13.3.2

Resetting the Device

Driving the CE pin from a low to a high can reset the device (CE reset).

There is another type of reset, which is a power-on reset. It occurs when supply voltage VDD is turned on.

See Chapter 14 for details.

13.3.3

Signal Inputs to the CE Pin

The CE pin does not accept a high or low level with a duration of less than 187.5

µs to prevent malfunction

due to noise.

The input level of a signal supplied to the CE pin is checked using the CE flag in the control register (bit

b0 at address 07H).

Fig. 13-2 shows the relationship between the input signal and CE flag.

Fig. 13-2

Relationship Between the Input Signal and CE Flag

CE pin

CE flag

Less than 187.5 s

CE reset

STOP instruction disabled (NOP)

STOP instruction enabled

STOP instruction disabled (NOP);

a CE reset occurs next time

the timer carry FF is set.

187.5 s

µµ

UPD17062 데이터시트(PDF) 157 Page - Renesas Technology Corp