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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPD17062 데이터시트(PDF) 233 Page - Renesas Technology Corp |
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UPD17062 데이터시트(HTML) 233 Page - Renesas Technology Corp |
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233 / 298 page  231 µPD17062 18.6 PLL DISABLE MODE The PLL frequency synthesizer is disabled when the CE pin is at a low level. It is also disabled when the PLL reference mode select register (PLRFMODE, at address 13H) selects the PLL disable mode. Table 18-1 summarizes how each block operates during the PLL disable mode. Because the PLL reference mode select register is not initialized at a CE reset (its previous state is preserved), it returns to the previous state after the CE pin goes low (selecting the PLL disable mode) then back to a high. If it is necessary to select the PLL disable mode at a CE reset, the PLL reference mode select register should be initialized by program. The PLL frequency synthesizer is disabled at a power-on reset. Table 18-1 Operation of Each Block During the PLL Disable Mode Block CE pin = low or PLRFMODE = 1111B VCO pin Pulled down internally Programmable counter Frequency division disabled Reference frequency generator Output disabled Phase comparator Output disabled Charge pump Error output pin floating |
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