AVR32AP datasheet(7/181 Pages) ATMEL

7 / 181 page

32001A–AVR32–06/06

AVR32

2.4

Status register configuration

The Status Register (SR) is splitted into two halfwords, one upper and one lower. The lower

word contains the C, Z, N, V and Q condition code flags and the R, T and L bits, while the upper

halfword contains information about the mode and state the processor executes in.

Figure 2-2.

The Status Register high halfword.

Figure 2-3.

The Status Register low halfword.

H - Java Handle

This bit is included to support different heap types in the Java Virtual Machine. For more details,

see the Java Technical Reference manual. The bit is cleared at reset.

J - Java state

The processor is in Java state when this bit is set. The incoming instruction stream will be

decoded as a stream of Java bytecodes, not RISC opcodes. The bit is cleared at reset. This bit

should not be modified by the user as undefined behaviour may result.

DM - Debug State Mask

If this bit is set, the Debug State is masked and cannot be entered. The bit is cleared at reset,

and can both be read and written by software.

Bit 3 1

Bit 1 6

In te rru pt Le ve l 0 M a sk

In te rru pt Le ve l 1 M a sk

In te rru pt Le ve l 3 M a sk

In te rru pt Le ve l 2 M a sk

Re se rve d

I0 M

I2 M

In itia l va lu e

Bit n a m e

I1 M

M o d e B it 0

M o d e B it 1

M o d e B it 2

Re se rve d

De b u g S ta te

I3 M

Ja va S ta te

Exce p tio n M a s k

G lo b a l In te rru p t M a sk

D e b u g S tate M a sk

Ja va H a n d le

Re se rve d

Bit 1 5

Bit 0

Re s e rv e d

C a rry

Ze ro

Sig n

B it nam e

In itia l v a lu e

Ov e rflo w

S a tu ra tio n

Lo c k

R e g is ter R e m a p E n ab le

Sc ra tc h

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