AVR32AP datasheet(14/181 Pages) ATMEL

14 / 181 page

32001A–AVR32–06/06

AVR32

The COUNT register will increment even though a compare interrupt is pending.

COMPARE - Cycle Counter Compare Register

The COMPARE register holds a value that the COUNT register is compared against. The COM-

PARE register can both be read and written. When the COMPARE and COUNT registers match,

a compare interrupt request is generated. This interrupt request is routed out to the interrupt

controller, which may forward the request back to the processor as a normal interrupt request at

a priority level determined by the interrupt controller. Writing a value to the COMPARE register

clears any pending compare interrupt requests. The compare and exception generation feature

is disabled if the COMPARE register contains the value zero. The COMPARE register is written

to zero upon reset.

TLBEHI - MMU TLB Entry Register High Part

Used to interface the CPU to the TLB. The contents and functionality of the register is described

in detail in Section 4. on page 48.

TLBELO - MMU TLB Entry Register Low Part

Used to interface the CPU to the TLB. The contents and functionality of the register is described

in detail in Section 4. on page 48.

PTBR - MMU Page Table Base Register

Contains a pointer to the start of the Page Table. The contents and functionality of the register is

described in detail in Section 4. on page 48.

TLBEAR - MMU TLB Exception Address Register

Contains the virtual address that caused the most recent MMU error. The contents and function-

ality of the register is described in detail in Section 4. on page 48.

MMUCR - MMU Control Register

Used to control the MMU and the TLB. The contents and functionality of the register is described

in detail in Section 4. on page 48.

TLBARLO/HI - MMU TLB Accessed Register Low/High

Contains the Accessed bits for the TLB. The contents and functionality of the register is

described in detail in Section 4. on page 48.

PCCNT - Performance Clock Counter

Clock cycle counter for performance counters. The contents and functionality of the register is

described in detail in the AVR32 Architecture Manual.

PCNT0 / PCNT1 - Performance Counter 0 / 1

Counts the events specified by the Performance Counter Control Register. The contents and

functionality of the register is described in detail in the AVR32 Architecture Manual.

PCCR - Performance Counter Control Register

Controls and configures the setup of the performance counters. The contents and functionality

of the register is described in detail in the AVR32 Architecture Manual.

BEAR - Bus Error Address Register

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