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AVR32AP 데이터시트(PDF) 75 Page - ATMEL Corporation |
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AVR32AP 데이터시트(HTML) 75 Page - ATMEL Corporation |
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75 / 181 page ![]() 75 32001A–AVR32–06/06 AVR32 7.2 Write buffer behaviour Reset invalidates the entire write buffer. Writes are separated into "write now" (unbufferable) and "write later" (bufferable) writes. Multiple bufferable writes to the same aligned 32-byte line may be merged for performance, and reads may forward buffered data directely from the buffer. Bufferable writes will stay in the write buffer until forced out when one of the following occur: A buffered write is to another 32-byte line than the one currently in the buffer. The old data are moved to the "write now" part of the buffer, and the new data are kept as "write later". A read finds only part of the requested data in the write buffer, e.g a word read finds one byte of the word in the write buffer. The buffered data are moved to the "write now" part of the buffer, and the read is qued until the write has completed. This ensures data consistency. A SYNC instruction is executed. All data in the write buffer are written to the bus. Unbufferable writes are put in the "write now" part of the buffer. These are written to the bus at the earliest oportunity, in the same order as issued, and without any write combining. These data cannot be forwarded by reads, and are always performed before any read misses. 7.3 Cache and write buffer operations 7.3.1 The Cache instruction The cache instruction can be used to send special commands to the cache with a 32-bit param- eter. Se the architecture reference manual for description of the instruction. The following commands are currently defined: Table 7-1. Cache instruction parameters Op[4:3] Op[2:0] Operation Parameter 01 000 Flush Flush Mode 01 001 Lock Virtual Address 01 010 Unlock Virtual Address 01 011 Invalidate Virtual Address 01 100 Clean Virtual Address 01 101 Clean & Invalidate Virtual Address 01 110 Reserved for future use Undefined 01 111 Reserved for future use Undefined Other xxx Reserved for other caches N/A |
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