AVR32AP datasheet(4/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

1.5

Microarchitectures

The AVR32 architecture defines different microarchitectures. This enables implementations that

are tailored to specific needs and applications. The microarchitectures provide different perfor-

mance levels at the expense of area and power consumption. The following microarchitectures

are defined:

1.5.1

AVR32A

The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller

microcontrollers. This microarchitecture does not provide dedicated hardware registers for shad-

owing of register file registers in interrupt contexts. Additionally, it does not provide hardware

registers for the return address registers and return status registers. Instead, all this information

is stored on the system stack. This saves chip area at the expense of slower interrupt handling.

Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These

registers are pushed regardless of the priority level of the pending interrupt. The return address

and status register are also automatically pushed to stack. The interrupt handler can therefore

use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are

restored, and execution continues at the return address stored popped from stack.

The stack is also used to store the status register and return address for exceptions and scall.

Executing the rete or rets instruction at the completion of an exception or system call will pop

this status register and continue execution at the popped return address.

1.5.2

AVR32B

The AVR32B microarchitecture is targeted at applications where interrupt latency is important.

The AVR32B therefore implements dedicated registers to hold the status register and return

address for interrupts, exceptions and supervisor calls. This information does not need to be

written to the stack, and latency is therefore reduced. Additionally, AVR32B allows hardware

shadowing of the registers in the register file. The INT0 to INT3 contexts may have dedicated

versions of the registers in the register file, allowing the interrupt routine to start executing

immediately.

The scall, rete and rets instructions use the dedicated status register and return address regis-

ters in their operation. No stack accesses are performed.

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