AVR32AP datasheet(21/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

Pipeline

3.1

Overview

AVR32 AP is a pipelined processor with seven pipeline stages. The pipeline has three subpipes,

namely the Multiply pipe, the Execute pipe and the Data pipe. These pipelines may execute dif-

ferent instructions in parallel. Instructions are issued in order, but may complete out of order

(OOO) since the subpipes may be stalled individually, and certain operations may use a subpipe

for several clock cycles.

The following figure shows an overview of the AVR32 AP pipeline stages.

Figure 3-1.

The AVR32 AP pipeline stages.

The following abbreviations are used in the figure:

• IF1, IF2 - Instruction Fetch 1 and 2

• ID - Instruction Decode

• IS - Instruction Issue

• A1, A2 - ALU stage 1 and 2

• M1, M2 - Multiply stage 1 and 2

• DA - Data Address calculation stage

• D - Data cache access

• WB - Writeback

3.2

Prefetch unit

The prefetch unit comprises the IF1 and IF2 pipestages, and is responsible for feeding instruc-

tions to the decode unit. The prefetch unit fetches 32 bits at a time from the instruction cache

and places them in a FIFO prefetch buffer. At the same time, one instruction, either RISC

extended or compact, or Java, is fed to the decode stage.

The instruction fetches are probed for the presence of change-of-flow instructions. If such

instructions are found, the prefetch unit will try to determine the destination of the instruction and

continue fetching instructions from there. The branch penalty will be eliminated if the prefetch

unit correctly predicts the destination of a change-of-flow instruction. When possible, the

IF2

Prefetch unit

Decode unit

ALU pipe

Multiply pipe

Load-store

pipe

IF1

AVR32AP 데이터시트(PDF) 21 Page - ATMEL Corporation