AVR32AP datasheet(47/181 Pages) ATMEL

47 / 181 page

32001A–AVR32–06/06

AVR32

3.13

Processor consistency

Special hardware is implemented ensuring strict processor consistency, despite the use of OOO

completion. No instruction is allowed to change the state of the processor if there is a possibility

that an older, uncommitted instruction may not complete. In such a case, the younger instruction

is frozen in the IS stage until it can be guaranteed that the older instruction will commit. In prac-

tice, it is only memory access instructions that can cause a recoverable exception after they

have left the IS stage. Such address-related exceptions are always detected at the end of the D

stage. All other exceptions occuring after an instruction has left the IS stage are unrecoverable,

so processor consistency is unimportant, as a reset will have to be performed anyway.

The following mechanisms ensure processor consistency:

3.13.1

Address boundary checking

If a memory access instruction generates addresses that cross a page boundary, the next

sequential instruction is frozen in the IS stage until the memory access instruction has success-

fully left the D stage. This ensures that no address-related exceptions will occur in the middle of

a memory access instruction. As a consequence, the memory access instruction is guaranteed

to complete, and the following instruction may safely leave the IS stage.

Simple address checking is used to ensure that a memory access instruction cannot cause an

address related exception. This is checked by examining the memory pointer, the size of the

data transfer and the direction of pointer incrementation.

3.13.2

Handling contaminated instructions

Contaminated instructions are instructions that are tagged as having caused an exception. The

following rules ensures in-order completion and handling of contaminated instructions.

• A contaminated instruction is frozen in the IS stage until the DA and D stages are empty.

• When a contaminated instruction leaves the IS stage, it is issued to the A1 stage, regardless

of instruction type. All sequential instructions are frozen until the contaminated instruction

has either committed or been flushed from the pipe. This last event can occur only when the

contaminated instruction is folded with a branch.

3.13.3

Handling instructions with PC as destination

Instructions with PC as destination register will cause a change of flow. It must therefore be

ensured that no sequential instructions are allowed to commit before the instruction updating the

PC. When the instruction updating PC has left IS, all upstream stages are frozen until the

instruction updating PC has committed. The new PC value is forwarded directly from the WB

stage to the IF stage.

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