AVR32AP datasheet(63/181 Pages) ATMEL

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32001A–AVR32–06/06

AVR32

Prefetch Unit

5.1

Instruction buffer

The instruction buffer is implemented as a 96-bit FIFO queue, holding 12 byte-sized entries. The

buffer can hold either Java or RISC instructions. The instruction at the front of the queue is

issued to the ID stage at each clock cycle. The buffer detects the length of this instruction, and

shifts the queue the appropriate amount. The tail of the queue is filled with instructions from the

instruction cache. Instructions are placed in the buffer as soon as the queue has vacant slots. If

the queue is empty, or the instruction at the head of the queue is only partially fetched, the ID

stage may need to stall until the entire instruction is available.

The queue can contain instructions of different length. The instruction at the front of the queue is

always assumed to be a valid, aligned and complete instruction. If this condition fails, the hard-

ware would be unable to determine the instruction boundary. This is necessary in order to

separate between instructions and decide where in the buffer an instruction starts and ends.

The instruction buffer has the following format:

Figure 5-1.

Instruction buffer.

5.1.1

Instruction buffer fill

If the instruction buffer is non-empty, fetched instructions will always reside at sequential

addresses of the instructions already in the buffer. In this case, no special concerns are taken. If

the instruction buffer has been flushed and is empty, the loaded word must be rotated in such a

way that the addressed instruction is placed at the front of the instruction queue. If the target

address is not word-aligned, the most significant bytes in the fetched word are discarded. In

order to efficiently execute branch instructions, the branch targets for extended branch target

instructions should be aligned. This will in many cases allow the target instruction to be fetched

and executed without pipeline stalls.

A dedicated fetch address adder generates addresses to fetch from the instruction cache for

sequential instruction flow.

5.1.2

Flushing of the instruction buffer

The instruction buffer is flushed in the following circumstances:

• Entry into an exception routine

• Execution of an instruction with PC as target register

• Excecution of an unpredicted branch

• Detection of a mispredicted branch

• A procedure return address is popped from the return address stack.

Instru ctio n qu eu e

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