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AVR32AP 데이터시트(PDF) 46 Page - ATMEL Corporation

부품명 AVR32AP
상세설명  32-bit AVR Microcontroller
PDF  181 Pages
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제조업체  ATMEL [ATMEL Corporation]
홈페이지  http://www.atmel.com
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AVR32AP 데이터시트(HTML) 46 Page - ATMEL Corporation

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32001A–AVR32–06/06
AVR32
3.12
Interrupt latencies
The following features in AVR32 AP ensure low and deterministic interrupt latency:
• Four different interrupt levels and an NMI ensures that the user can efficiently prioritize the
interrupt sources.
• Interrupts are autovectored, allowing the CPU to jump directly to the interrupt handler.
• A shadowed interrupt context for INT3 is provided so that critical interrupt handlers can start
directly without having to stack registers.
• Interrupt handler code can be locked in the icache, and the corresponding page table
information can be locked in the TLB.
The following calculations makes the following assumptions:
• The interrupt handler code is present in the icache and fetching handler instructions does not
cause any MMU exceptions.
• The pending interrupt is of higher priority than any executing interrupts, so that it can be
handled immediately.
• Any instructions in DA or D do not cause a cache miss. Any interrupts will wait until
instructions in DA or D have left these pipeline stages. If the instruction in DA or D cause a
cache miss, the time for the cache line to be loaded so that the instruction can complete will
depend on the timing of the memory the data will be loaded from. Any time spent reloading a
cache line must be added to the maximum interrupt latency calculated below.
3.12.1
Maximum interrupt latency
The maximum interrupt latency occurs when a long-running instruction is present in DA. Any
instruction must have left DA and D before interrupt handling will commence. The latency can be
calculated as follows:
3.12.2
Minimum interrupt latency
The maximum interrupt latency can be calculated as follows:
Table 3-4.
Maximum interrupt latency
Source
Delay
Wait for the slowest instruction (ldm/stm) to leave DA and D
10
Wait for autovector target instruction to be fetched
4
TOTAL
14
Table 3-5.
Maximum interrupt latency
Source
Delay
DA and D are empty
0
Wait for autovector target instruction to be fetched
4
TOTAL
4



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