ADC3683 datasheet(17/70 Pages) TI1

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7.3.1.1 Analog Front End Design

The ADC3683-SP is an unbuffered ADC, so a passive kick-back filter is recommended to absorb the glitch from

the sampling operation. If the input is driven by a balun or a differential amplifier with low output impedance, a

termination network may be needed. Additionally, a passive DC bias circuit is needed in AC-coupled applications

which can be combined with the termination network.

For more details and information on analog front end design, see Unraveling the practical mysteries behind RF

converter front ends.

7.3.1.1.1 Sampling Glitch Filter Design

The front end sampling glitch filter is designed to optimize the SNR and HD3 performance of the ADC. The

filter performance is dependent on input frequency: therefore, the following filter designs are recommended for

different input frequency ranges as shown in Figure 7-2 and Figure 7-3 (assuming a 50Ω source impedance).

100 pF

180nH

Termination

Figure 7-2. Sampling Glitch Filter Example for Input Frequencies From DC to 30MHz

Termination

82 pF

120nH

100pF

120nH

100pF

Figure 7-3. Sampling Glitch Filter Example for Input Frequencies From 30 to 70MHz

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ADC3683-SP

SBASAB5 – MARCH 2024

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ADC3683 데이터시트(PDF) 17 Page - Texas Instruments