ADC3683 datasheet(11/70 Pages) TI1

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5.8 Timing Requirements (continued)

Typical values are at TA = 25°C, MIN and MAX timing values are characterized over the full temperature range TMIN = –55°C

to TMAX = 105°C and are NOT production tested, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD =

1.8 V, 1.6 V external reference, and –1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

Interface Timing: Serial LVDS Interface

tPD

Propagation delay: sampling clock

falling edge to DCLK rising edge

Delay between sampling clock falling edge to

DCLKIN falling edge < 2.5ns.

TDCLK = DCLK period

tCDCLK = Sampling clock falling edge to DCLKIN

falling edge

2 +

TDCLK

tCDCLK

3 +

TDCLK

tCDCLK

4 +

TDCLK

tCDCLK

Delay between sampling clock falling edge to

DCLKIN falling edge >= 2.5ns.

TDCLK = DCLK period

tCDCLK = Sampling clock falling edge to DCLKIN

falling edge

2 +

tCDCLK

3 +

tCDCLK

4 +

tCDCLK

tCD

DCLK rising edge to output data

delay,

2-wire SLVDS

Fout = 10 MSPS, DA/B0,1 = 90 MBPS

0.1

Fout = 65 MSPS, DA/B0,1 = 585 MBPS

0.1

DCLK rising edge to output data

delay,

1-wire SLVDS

Fout = 10 MSPS, DA/B0 = 180 MBPS

0.1

0.2

Fout = 55 MSPS, DA/B0 = 990 MBPS

-0.4

0.1

DCLK rising edge to output data

delay,

1/2-wire SLVDS

Fout = 5 MSPS, DA0 = 180 MBPS

0.1

Fout = 25 MSPS, DA0 = 720 MBPS

0.1

tDV

Data valid, 2-wire SLVDS

Fout = 10 MSPS, DA/B0,1 = 90 MBPS

10.5

10.7

Fout = 65 MSPS, DA/B0,1 = 585 MBPS

1.3

1.4

Data valid, 1-wire SLVDS

Fout = 10 MSPS, DA/B0 = 180 MBPS

4.7

4.8

Fout = 55 MSPS, DA/B0 = 990 MBPS

0.5

0.6

Data valid, 1/2-wire SLVDS

Fout = 5 MSPS, DA0 = 180 MBPS

4.7

4.8

Fout = 25 MSPS, DA0 = 900 MBPS

0.6

0.7

SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input

fCLK(SCLK)

Serial clock frequency

MHz

tSU(SEN)

SEN to rising edge of SCLK

tH(SEN)

SEN from rising edge of SCLK

tSU(SDIO)

SDIO to rising edge of SCLK

tH(SDIO)

SDIO from rising edge of SCLK

SERIAL PROGRAMMING INTERFACE (SDIO) - Output

t(OZD)

SDIO output to driven

t(ODZ)

SDIO data to output

t(OD)

SDIO valid from falling edge of SCLK

(1)

Max value allowed and does not scale with sample rates.

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ADC3683-SP

SBASAB5 – MARCH 2024

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