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ADC3683 데이터시트(PDF) 31 Page - Texas Instruments

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부품명 ADC3683
상세설명  ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC
PDF  70 Pages
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7.3.4.7 Output Formatting with Decimation
When using decimation, the digital output data is formatted as shown in Figure 7-34 (complex decimation) and
Figure 7-35 (real decimation). The output format is shown for 18-bit output resolution.
FCLK
Serial LVDS
1-Wire
(18x Serialization)
Serial LVDS
2-Wire
(9x Serialization)
DA1
DA0
DB1
DB0
ChA
ChB
Serial LVDS
1/2-Wire
(36x Serialization)
FCLK
DA0
DB0
FCLK
DA0
DCLK
DCLK
DCLK
BI <17:0>
AI <17:0>
AQ <17:0>
BQ <17:0>
AI <17:0>
BI <17:0>
BQ <17:0>
AQ <17:0>
BI
D13
BI
D11
BI
D9
BI
D7
BI
D5
BI
D3
BI
D1
BI
D12
BI
D10
BI
D8
BI
D6
BI
D4
BI
D2
BI
D0
BQ
D13
BQ
D11
BQ
D9
BQ
D7
BQ
D5
BQ
D3
BQ
D12
BQ
D10
BQ
D8
BQ
D6
BQ
D4
BQ
D2
BQ
D1
BQ
D0
AI
D13
AI
D11
AI
D9
AI
D7
AI
D5
AI
D3
AI
D1
AI
D12
AI
D10
AI
D8
AI
D6
AI
D4
AI
D2
AI
D0
AQ
D13
AQ
D11
AQ
D9
AQ
D7
AQ
D5
AQ
D3
AQ
D12
AQ
D10
AQ
D8
AQ
D6
AQ
D4
AQ
D2
AQ
D1
AQ
D0
BI
D17
BI
D15
BI
D16
BI
D14
AI
D17
AI
D15
AI
D16
AI
D14
BQ
D17
BQ
D15
BQ
D16
BQ
D14
AQ
D17
AQ
D15
AQ
D16
AQ
D14
Figure 7-34. Output Data Format in Complex Decimation (18-bit Output Resolution)
Table 7-4 shows the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK
frequencies based on output resolution (R), number of SLVDS lanes (L) and complex decimation setting (N).
Table 7-4 shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 18-bit output resolution and
complex decimation by 4.
Table 7-4. Serial LVDS Lane Rate Examples with Complex Decimation and 18-bit Output Resolution
DECIMATION
SETTING
ADC SAMPLING
RATE
OUTPUT
RESOLUTION
# of WIRES
FCLK
DCLKIN, DCLK
DA/B0,1
N
FS
R
L
FS / N
[DA/B0,1] / 2
FS x 2 x R / L / N
4
65MSPS
18
2
16.25MHz
146.25 MHz
292.5 MHz
1
292.5 MHz
585 MHz
55MSPS
1/2
13.75MHz
495 MHz
990 MHz
www.ti.com
ADC3683-SP
SBASAB5 – MARCH 2024
Copyright © 2024 Texas Instruments Incorporated
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