ADC3683 datasheet(34/70 Pages) TI1

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7.3.5.2 Output Scrambler

The device includes an optional output scrambler feature. Scrambling is performed on each serial output lane

independently. When enabled, the serial output bit stream is scrambled where each output bit is XOR-ed with

2 previous bits (k-14 and k-15) as shown in Figure 7-38. For descrambling, note that the output bit mapper is

located after the scrambler.

On the external receiver, the incoming serial data stream can be descrambled by XOR-ing each incoming bit

with 2 previous bits (k-14 and k-15).

Lane 0

Lane 1

Digital

Scrambler

Bit Mapper

Figure 7-37. Output scrambling per lane

Scrambling is enabled by disabling digital bypass (register 0x24, D2) and enabling scrambling (register 0x22,

D6).

XOR

Serial bit stream

x[k]

-1

y[k-1]

-1

y[k-2]

-1

...

y[k-15]

-1

y[k-14]

-1

Serial output bit stream

y[k]

XOR

-1

y[k-1]

-1

y[k-2]

-1

...

-1

y[k-14]

-1

y[k-15]

Serial bit stream

x[k]

Scrambler

De-Scrambler

Figure 7-38. Output scrambler and descrambler operation

ADC3683-SP

SBASAB5 – MARCH 2024

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