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부품명 ADC3683
상세설명  ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC
PDF  70 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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ADC3683 데이터시트(HTML) 50 Page - Texas Instruments

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8.5.2 Layout Example
The following screen shot shows the top layer of the ADC3683EVM (QFN package). The same layout
recommendation apply to the device.
• Signal and clock inputs are routed as differential signals on the top layer avoiding vias.
• SLVDS output interface lanes are routed differential and length matched
• Bypass caps are close to the VREF pin on the top layer avoiding vias.
SLVDS routed tightly
coupled and length matched
Bypass caps on VREF close
to the pins and no vias
Analog inputs on
top layer (no vias)
Clock routing
without vias
Figure 8-10. Layout example: top layer of ADC3683EVM
ADC3683-SP
SBASAB5 – MARCH 2024
www.ti.com
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Product Folder Links: ADC3683-SP



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