ADC3683 datasheet(10/70 Pages) TI1

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5.8 Timing Requirements

Typical values are at TA = 25°C, MIN and MAX timing values are characterized over the full temperature range TMIN = –55°C

to TMAX = 105°C and are NOT production tested, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD =

1.8 V, 1.6 V external reference, and –1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

ADC Timing Specifications

tAD

Aperture Delay

0.85

Aperture Jitter

Square wave clock with fast edges

180

Jitter on DCLKIN

50 (1)

tACQ

Signal acquisition period, referenced

to sampling clock falling edge

FS = 10 Msps

-TS/2

Sampling

Clock

Period

FS = 25 Msps

-TS/2

FS = 65 Msps

-TS/4

tCONV

Signal conversion period, referenced

to sampling clock falling edge

FS = 10 Msps

+TS ×

1/5

Sampling

Clock

Period

FS = 25 Msps

+TS ×

3/8

FS = 65 Msps

+TS ×

5/8

Wake up

time

Time to valid data after coming out of

power down. Internal reference.

Bandgap reference enabled, single ended clock

Bandgap reference enabled, differential clock

Bandgap reference disabled, single ended clock

Bandgap reference disabled, differential clock

Time to valid data after coming out of

power down.

External 1.6V reference.

Bandgap reference enabled, single ended clock

Bandgap reference enabled, differential clock

100

Bandgap reference disabled, single ended clock

Bandgap reference disabled, differential clock

tS,SYNC

Setup time for SYNC input signal

Referenced to sampling clock rising edge

500

tH,SYNC

Hold time for SYNC input signal

600

ADC

Latency

Signal input to data output

SLVDS 2-wire

ADC

clock

cycles

SLVDS 1-wire

SLVDS 1/2-wire

Add

Latency

Real decimation by 2

Output

clock

cycles

Complex decimation by 2

Real or complex decimation by 4, 8, 16, 32

ADC3683-SP

SBASAB5 – MARCH 2024

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