MPC8555CPXAPF datasheet(28/88 Pages) FREESCALE

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MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Three-Speed, MII Management

8.2.4

TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

8.2.4.1

TBI Transmit AC Timing Specifications

Table 24 provides the MII transmit AC timing specifications.

Figure 11 shows the TBI transmit AC timing diagram.

Figure 11. TBI Transmit AC Timing Diagram

Table 24. TBI Transmit AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

GTX_CLK clock period

tTTX

—8.0

—

GTX_CLK duty cycle

tTTXH/tTTX

—

GMII data TCG[9:0], TX_ER, TX_EN setup time

GTX_CLK going high

tTTKHDV

2.0

—

GMII data TCG[9:0], TX_ER, TX_EN hold time from

GTX_CLK going high

tTTKHDX

1.0

—

GTX_CLK clock rise and fall time

tTTXR, tTTXF

2,3

——

1.0

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state

)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV

symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data

signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the

time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in

general, the clock reference symbol representation is based on three letters representing the clock of a particular

functional. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.

3. Guaranteed by design.

GTX_CLK

TCG[9:0]

tTTXR

tTTX

tTTXH

tTTXR

tTTXF

tTTKHDV

tTTKHDX

tTTXF

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