MPC8555CPXAPF datasheet(68/88 Pages) FREESCALE

68 / 88 page

MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Thermal

16 Thermal

This section describes the thermal specifications of the MPC8555E.

16.1

Thermal Characteristics

Table 49 provides the package thermal characteristics for the MPC8555E.

16.2

Thermal Management Information

This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA)

package for air-cooled applications. Proper thermal control design is primarily dependent on the

system-level design—the heat sink, airflow, and thermal interface material. The recommended attachment

method to the heat sink is illustrated in Figure 42. The heat sink should be attached to the printed-circuit

board with the spring force centered over the die. This spring force should not exceed 10 pounds force.

Table 49. Package Thermal Characteristics

Characteristic

Symbol

Value

Unit

Notes

Junction-to-ambient Natural Convection on four layer board (2s2p)

RθJMA

°C/W

1, 2

Junction-to-ambient (@200 ft/min or 1.0 m/s) on four layer board (2s2p)

RθJMA

°C/W

1, 2

Junction-to-ambient (@400 ft/min or 2.0 m/s) on four layer board (2s2p)

RθJMA

•C/W

1, 2

Junction-to-board thermal

RθJB

•C/W

Junction-to-case thermal

RθJC

0.96

•C/W

Notes

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance

2. Per JEDEC JESD51-6 with the board horizontal.

3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1). Cold plate temperature is used for case temperature; measured value includes the thermal resistance of the

interface layer.

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