MPC8555CPXAPF datasheet(83/88 Pages) FREESCALE

83 / 88 page

MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

System Design Information

Figure 52. JTAG Interface Connection

HRESET

From Target

Board Sources

COP_HRESET

COP_SRESET

SRESET

COP_VDD_SENSE2

10 k

COP_CHKSTP_IN

CKSTP_IN

COP_TMS

COP_TDO

COP_TDI

COP_TCK

TMS

TDO

TDI

COP_TRST

(if any)

14 3

Notes:

3. The KEY location (pin 14) is not physically present on the COP header.

10 k

TRST1

10 k

CKSTP_OUT

COP_CHKSTP_OUT

KEY

No pin

COP Connector

Physical Pinout

SRESET

2. Populate this with a 10

Ω resistor for short-circuit/current-limiting protection.

OVDD

10 k

HRESET1

in order to fully control the processor as shown here.

4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for

1. The COP port and target board should be able to independently assert HRESET and TRST to the processor

improved signal integrity.

TCK

5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid

accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.

10 k

6. Asserting SRESET causes a machine check interrupt to the e500 core.

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