MPC8555CPXAPF datasheet(67/88 Pages) FREESCALE

부품명	MPC8555CPXAPF

상세설명	PowerQUICC??III Integrated Communications Processor Hardware Specifications

PDF	88 Pages

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제조업체	FREESCALE [Freescale Semiconductor, Inc]

홈페이지	http://www.freescale.com

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MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Clocking

15.3

e500 Core PLL Ratio

Table 47 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This

ratio is determined by the binary value of LALE and LGPL2 at power up, as shown in Table 47.

15.4

Frequency Options

Table 48 shows the expected frequency values for the platform frequency when using a CCB to SYSCLK

ratio in comparison to the memory bus speed.

Table 47. e500 Core to CCB Ratio

Binary Value of

LALE, LGPL2 Signals

Ratio Description

2:1 e500 core:CCB

5:2 e500 core:CCB

3:1 e500 core:CCB

7:2 e500 core:CCB

Table 48. Frequency Options with Respect to Memory Bus Speeds

CCB to SYSCLK

Ratio

SYSCLK (MHz)

100

111

133

Platform/CCB Frequency (MHz)

200

222

267

200

250

300

333

267

333

208

333

200

250

200

267

333

225

300

250

333

200

300

267

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