TMP93CS32F datasheet(37/180 Pages) TOSHIBA

37 / 180 page

TMP93CS32

2004-02-10

93CS32-35

3.4.3

Interrupt Controller

Figure 3.4.4 is a block diagram of the interrupt circuits. The left half of the diagram

shows the interrupt controller; the right half includes the CPU interrupt request signal

circuit and the halt release signal circuit.

Each interrupt channel (Total of 22 channels) in the interrupt controller has an interrupt

request flip-flop, interrupt priority setting register, and a register for storing the micro

DMA start vector. The interrupt request fip-flop is used to latch interrupt requests from

peripheral devices.

The flip-flop is cleared to 0 at reset, when the CPU reads the interrupt channel vector

after the acceptance of interrupt, or when the CPU executes an instruction that clears the

interrupt of that channel (Writes 0 in the clear bit of the interrupt priority setting register).

For example, to clear the INT0 interrupt request, set the register after the DI instruction

as follows.

(INTE0AD), - - - - 0 - - - B

The status of the interrupt request flip-flop is detected by reading the clear bit. Detects

whether there is an interrupt request for an interrupt channel.

The interrupt priority can be set by writing the priority in the interrupt priority setting

to be set are from 1 to 6. Writing 0 or 7 as the interrupt priority disables the corresponding

interrupt request. The priority of the non-maskable interrupt ( NMI pin, watchdog timer,

etc.) is fixed to 7. If interrupt requests with the same interrupt level are generated

simultaneously, interrupts are accepted in accordance with the default priority (The

smaller the vector value, the higher the priority).

The interrupt controller sends the interrupt request with the highest priority among the

simultaneous interrupts and its vector address to the CPU. The CPU compares the priority

value <IFF2:0> set in the Status Register by the interrupt request signal with the priority

value sent; if the latter is higher, the interrupt is accepted. Then the CPU sets a value

higher than the priority value by 1 in the CPU SR<IFF2:0>. Interrupt requests where the

priority value equals or is higher than the set value are accepted simultaneously during the

previous interrupt routine. When interrupt processing is completed (after execution of the

RETI instruction), the CPU restores the priority value saved in the stack before the

interrupt was generated to the CPU SR<IFF2:0>.

The interrupt controller also has four registers used to store the Micro DMA start vector.

These are I/O registers; unlike other micro DMA registers (DMAS, DMAD, DMAM, and

DMAC). Writing the start vector of the interrupt source for the micro DMA processing (see

Table 3.4.1), enables the corresponding interrupt to be processed by micro DMA processing.

The values must be set in the micro DMA parameter registers (e.g., DMAS and DMAD)

prior to the micro DMA processing.

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