TMP93CS32F datasheet(65/180 Pages) TOSHIBA

65 / 180 page

TMP93CS32

2004-02-10

93CS32-63

3.6.4

Bus Width/Wait Control

An image of the actual Bus-width/Wait control is shown below. Out of the whole memory

area, address areas that can be specified are divided into four parts. Addresses from

000000H to 3FFFFFH are divided differently: 7F00H to 7FFFH is specified for WAITC0;

880H to 7FFFH, for WAITC1; and 8000H to 3FFFFFH, for WAITC2. The reason is that a

device other than ROM (e.g., RAM or I/O) might be connected externally.

7F00 to 7FFFH (256 bytes) for WAITC0 are mapped mainly for possible expansions to

external I/O.

880H to 7FFFH (Approx. 31 K bytes) for WAITC1 are mapped there mainly for possible

extensions to external RAM.

8000H to 3FFFFFH (Approx. 4 M bytes) for WAITC2 are mapped mainly for possible

extensions to external ROM. With the TMP93CS32 which has a built-in ROM, addresses

from FF0000H to FFFFFFH are used as the internal ROM area; WAITC2 is disabled in

this area. After reset, the CPU reads the program from the built-in ROM in 16-bit bus,

0-wait mode.

Note 1: Access priority is highest for built-in I/O, then built-in memory, and lowest for the bus

width/wait controller.

Note 2: External areas other than WAITC0 to WAITC2 are accessed in 16-bit data bus (0 waits)

mode.

When using the bus width/wait controller, do not specify the same address area more

than once.

(However, when addresses 7F00H to 7FFFH for WAITC0 and 880H to 7FFFH for

WAITC1 are specified, in other words, specifications overlap, only the WAITC0 setting

is active.)

000000H

7F00H

8000H

WAITC0

WAITC1

<B0C1:0>

= “00”

<B1C1:0>

= “00”

WAITC2

<B2C1:0>

= “00”

<B0C1:0>

= “01”

<B0C1:0>

= “10”

<B0C1:0>

= “11”

<B1C1:0>

= “01”

<B1C1:0>

= “10”

<B1C1:0>

= “11”

<B2C1:0>

= “01”

<B2C1:0>

= “10”

<B2C1:0>

= “11”

400000H

800000H

C00000H

FFFFFFH

(Mainly for I/O)

(Mainly for RAM)

(Mainly for ROM)

880H

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