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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMP93CS32F 데이터시트(PDF) 91 Page - Toshiba Semiconductor |
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TMP93CS32F 데이터시트(HTML) 91 Page - Toshiba Semiconductor |
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91 / 180 page  TMP93CS32 2004-02-10 93CS32-89 Timer 4 Mode Control Register 7 6 5 4 3 2 1 0 Bit symbol CAP1IN CAP12M1 CAP12M0 CLE T4CLK1 T4CLK0 T4MOD (0038H) Read/Write W R/W After reset 1 0 0 0 0 0 Function 0: Software capture 1: Don’t care Capture timing 00: Disable INT4 occurs at rising edge. 01: TI4 ↑ TI5 ↑ INT4 occurs at rising edge. 10: TI4 ↑ TI4 ↓ INT4 occurs at falling edge. 11: TFF1 ↑ TFF1↓ INT4 occurs at rising edge. 1: UC4 clear enable Timer 4 source clock 00: TI4 pin 01: φT1 10: φT4 11: φT16 Timer 4 input clock 00 External clock (TI4) 01 φT1 10 φT4 11 φT16 Clearing the up counter UC4 0 Clear disable 1 Clear by match with TREG5. Capture timing of timer 4 Capture control INT4 control 00 Capture disable 01 CAP1 at TI4 rise CAP2 at TI5 rise INT4 occurs on the rising edge of TI4. 10 CAP1 at TI4 rise CAP2 at TI4 fall INT4 occurs on the falling edge of TI4. 11 CAP1 at TFF1 rise CAP2 at TFF1 fall INT4 occurs on the rising edge of TI4. Software capture 0 The up counter 4 value is loaded to CAP1. 1 Don’t care Figure 3.8.3 16-Bit Timer/Event Counter Related Register (1/6) |
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