TMP93CS32F datasheet(81/180 Pages) TOSHIBA

81 / 180 page

TMP93CS32

2004-02-10

93CS32-79

3. Making timer 1 count up by match signal from timer 0 comparator

(Same function is achieved by using timer 3 and timer 2)

Set the 8-bit timer mode, and set the comparator output of timer 0 as the input clock

to timer 1.

Figure 3.7.11 Timer 1 Count up by Timer 0

(2) 16-bit timer mode

A 16-bit interval timer is configured by using the pair of timer 0 and timer 1 or timer 2

and timer 3.

To make a 16-bit interval timer by cascade connecting timer 0 and timer 1, set timer 1/0

mode register T10MOD<T10M1:0> to “01”.

When set in 16-bit timer mode, the overflow output of timer 0 and 2 will become the input

clock of timers 1 and 3, regardless of the set value of T10MOD<T1CLK1:0>and

T32MOD<T3CLK1:0>. Table 3.7.1 shows the relation between the cycle of timer (interrupt)

and the selection of input clock.

The lower 8 bits of the timer (Interrupt) cycle are set by the timer register TREG0 or

TREG2, and the upper 8 bits are set by TREG1 or TREG3. Note that TREG0 and TREG2

always must be set first. (Writing data into TREG0 and TREG2 disables the comparator

temporarily, and the comparator is restarted by writing data into TREG1 and TREG3.)

Setting example: To generate an interrupt INTT3 every 0.4 seconds at fc

= 20 MHz, set the following values for timer

registers TREG2 and TREG3.

* Clock Condition

Clock gear: 1 (fc)

Prescaler clock: fFPH

When counting with input clock of

φT16 (6.4 µs at 20 MHz)

0.4 s

÷ 6.4 µs = 62500 = F424H

Therefore, set TREG3

= F4H and TREG2 = 24H, respectively.

The comparator match signal is output from timer 2 each time the up counter UC2

matches TREG2, where the up counter UC2 is not be cleared, and the interrupt INTT2 is

not generated.

With the timer 3 comparator, the match detect signal is output at each comparator timing

when up counter UC3 and TREG3 values match. When the match detect signal is output

simultaneously from both comparators of timer 2 and timer 3, the up counters UC2 and

UC3 are cleared to “0”, and the interrupt INTT3 is generated. If inversion is enabled, the

value of the timer flip-flop TFF3 is inverted.

234

Comparator output

(Timer 0 match)

Timer 0 up counter

(when TREG0

= 5)

Timer 1 up counter

(when TREG1

= 2)

Timer 1 match output

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