TMP93CS32F datasheet(99/180 Pages) TOSHIBA

99 / 180 page

TMP93CS32

2004-02-10

93CS32-97

TREG4 timer register is of double buffer structure, which is paired with register buffer.

The timer control register T45CR<DB4EN> controls whether the double buffer structure

should be enabled or disabled: disabled when <DB4EN>

= 0, while enabled when

<DB4EN>

= 1.

When the double buffer is enabled, the timing to transfer data from the register buffer to

the timer register is at the match between the up counter (UC4) and timer register TREG5.

After reset, TREG4 and TREG5 are undefined. To use the 16-bit timer after reset, data

should be written beforehand.

When reset, it will be initialized to <DB4EN>

= 0, whereby the double buffer is disabled.

To use the double buffer, write data in the timer register, set <DB4EN>

= 1, and then write

the following data in the register buffer.

TREG4 and register buffer are allocated to the same memory addresses

000030H/000031H. When <DB4EN>

= 0, same value will be written in both the timer

= 1, the value is written into only the register

buffer. To write the initial-value to the timer register, the register buffer should be

disabled.

(4) Capture register

These 16-bit registers are used to latch the values of the up counter.

Data in the capture registers should be read all 16 bits. For example, using a 2-byte data

load instruction or two 1 byte data load instruction, from the lower 8 bits followed by the

upper 8 bits.

CAP 1 to CAP4 are read-only registers, so these registers cannot be written by software.

CAP 1

Timer 4

Upper 8 bits

Lower 8 bits

000035H

000034H

CAP 2

Upper 8 bits

Lower 8 bits

000037H

000036H

CAP 3

Timer 5

Upper 8 bits

Lower 8 bits

000045H

000044H

CAP 4

Upper 8 bits

Lower 8 bits

000047H

000046H

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