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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMP93CS32F 데이터시트(PDF) 20 Page - Toshiba Semiconductor |
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TMP93CS32F 데이터시트(HTML) 20 Page - Toshiba Semiconductor |
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20 / 180 page  TMP93CS32 2004-02-10 93CS32-18 Table 3.3.3 Halt Releasing Source and Halt Releasing Operation Interrupt Enable Interrupt Disable Interrupt Receiving Status (Interrupt level) ≥ (Interrupt mask) (Interrupt level) < (Interrupt mask) HALT Mode RUN IDLE2 IDLE1 STOP RUN IDLE2 IDLE1 STOP NMI ♦ ♦ ♦ ♦*1 − − − − INTWDT ♦ × × × − − − − INT0 ♦ ♦ ♦ ♦*1 ○ ○ ○ ○*1 INT4 to INT7 ♦ ♦ × × × × × × INTT0 to INTT3 ♦ ♦ × × × × × × INTTR4 to INTTR7 ♦ ♦ × × × × × × INTO4, INTO5 ♦ ♦ × × × × × × INTRX0, TX0 ♦ ♦ × × × × × × INTRX1, TX1 ♦ ♦ × × × × × × Interrupt INTAD ♦ × × × × × × × Halt releasing source RESET ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦: After releasing the HALT mode, CPU starts interrupt processing. (RESET initializes LSI.) ○: After releasing the HALT mode, CPU starts executing an instruction that follows the HALT instruction. ×: It can not be used to release the HALT mode. −: This combination type does not exist because the priority level (interrupt request level) of non-maskable interrupts is fixed to highest priority level “7”. *1: Releasing the HALT mode is executed after passing the warm-up time. Note: When releasing the HALT mode is executed by INT0 interrupt of the level mode in the interrupt enabled status, hold level “H” until starting interrupt processing. If level “L” is set, interrupt processing is correctly started. (Example releasing “RUN” mode) INT0 interrupt releases halt state when the RUN mode is on. Address 8203H LD (IIMC), 00H ; Selects INT0 interrupt rising edge. 8206H LD (INTE0AD), 06H ; Sets interrupt level to “6” for INT0. 8209H EI 5 ; Sets interrupt level to “5” for CPU. 820BH LD (WDMOD), 00H ; Sets HALT mode to “RUN”. 820EH HALT ; Halts CPU. INT0 INT0 Interrupt routine RETI 820FH LD XX, XX |
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