| 전자부품 데이터시트 검색엔진 |
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TMP93CS32F 데이터시트(PDF) 93 Page - Toshiba Semiconductor |
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TMP93CS32F 데이터시트(HTML) 93 Page - Toshiba Semiconductor |
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93 / 180 page ![]() TMP93CS32 2004-02-10 93CS32-91 Timer 5 Mode Control Register 7 6 5 4 3 2 1 0 Bit symbol CAP3IN CAP34M1 CAP34M0 CLE T5CLK1 T5CLK0 T5MOD (0048H) Read/Write W R/W After reset 1 0 0 0 0 0 Function Software capture control 0: Software capture 1: Don’t care Capture timing 00:Disable INT6 occurs on the rising edge. 01:TI6 ↑ TI7 ↑ INT6 occurs at rising edge. 10:TI6 ↑ TI6 ↓ INT6 occurs at falling edge. 11:TFF1 ↑ TFF1↓ INT4 occurs at rising edge. Timer 5 UC control 0: Clear disable 1: Clear enable Timer 5 source clock select 00: TI6 pin 01: φT1 10: φT4 11: φT16 Timer 5 input clock 00 External clock (TI6 pin input) 01 φT1 10 φT4 11 φT16 Clearing the up counter UC5 0 Clear disable 1 Clear by match with TREG7 Timer 5 capture timing Capture control INT6 control 00 Capture disable 01 CAP3 at TI6 rise CAP4 at TI7 rise INT6 occurs on the rising edge of TI6. 10 CAP3 at TI6 rise CAP4 at TI6 fall INT6 occurs on the falling edge of TI6. 11 CAP3 at TFF1 rise CAP4 at TFF1 fall INT6 occurs on the rising edge of TI6. Software capture 0 The up counter 5 value is loaded to CAP3. 1 Don’t care Figure 3.8.5 16-Bit Timer/Event Counter Related Register (3/6) |
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