TMP93CS32F datasheet(63/180 Pages) TOSHIBA

63 / 180 page

TMP93CS32

2004-02-10

93CS32-61

3.6.3

Bus Width/Wait Control Registers

Figure 3.6.1 shows control registers.

One block address areas are controlled by 1-byte bus width/wait control registers

(WAITC0, WAITC1, WAITC2).

(1) Data bus size select

Bit4 (<B0BUS>, <B1BUS>, <B2BUS>) of the control register is used to specify data

bus size. Setting this bit to 0 accesses the memory in 16-bit data bus mode; setting it to

1 accesses the memory in 8-bit data bus mode.

Changing data bus size depending on the access address is called dynamic bus sizing.

Table 3.6.1 shows the details of the bus operation.

(2) Wait control

Control register bits 3 and 2 (<B0W1:0>, <B1W1:0>, <B2W1:0>) are used to specify

the number of waits. These bits execute the following operation by setting.

“00” A2-state wait is inserted regardless of the WAIT pin status.

“01” A1-state wait is inserted regardless of the WAIT pin status.

“10” A1-state wait is inserted and the WAIT pin status is sampled. If the pin is low,

inserting the wait maintains the bus cycle until the pin goes high.

“11” The bus cycle is completed without a wait (0 waits) regardless of the WAIT pin

status.

After reset operation, clear to “00” (A2-state wait mode).

(3) Address area specification

Control register bits 1 and 0 (<B0C1:0>, <B1C1:0>, <B2C1:0>) are used to specify

the target address area. Setting these bits to 00 enables settings (Wait state, Bus size,

etc.) as follows:

WAITC0 setting enabled when 7F00H to 7FFFH is accessed.

WAITC1 setting enabled when 880H to 7FFFH is accessed.

WAITC2 setting enabled when 8000H to 3FFFFFH is accessed.

Setting bits to 01 enables setting for each block when 400000H to 7FFFFFH is

accessed. Setting bits to 10 enables them when 800000H to BFFFFFH is accessed.

Setting bits to 11 enables them when C00000H to FFFFFFH is accessed.

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