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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMP93CS32F 데이터시트(PDF) 133 Page - Toshiba Semiconductor |
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TMP93CS32F 데이터시트(HTML) 133 Page - Toshiba Semiconductor |
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133 / 180 page  TMP93CS32 2004-02-10 93CS32-131 Protocol 1. Select the 9-bit UART mode for the master and slave controllers. 2. Set SC0MOD<WU> bit of each slave controller to “1” to enable data receiving. 3. The master controller transmits one-frame data including the 8-bit select code for the slave controllers. The MSB (bit8) <TB8> is set to “1”. 4. Each slave controller receives the above frame, and clears WU bit to “0” if the above select code matches its own select code. 5. The master controller transmits data to the specified slave controller whose SC0MOD<WU> bit is cleared to “0”. The MSB (bit8) <TB8> is cleared to “0”. 6. The other slave controllers (with the <WU> bit remaining at “1”) ignore the receiving data because their MSBs (Bit8 or <RB8>) are set to “0” to disable the interrupt INTRX0. The slave controllers (<WU> = 0) can transmit data to the master controller, and it is possible to indicate the end of data receiving to the master controller by this transmission. Start Bit0 12 345 6 Data 7 Stop Bit8 “0” Start Bit0 12 345 6 Select code of slave controller 7 Stop 8 “1” |
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