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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMP93CS32F 데이터시트(PDF) 156 Page - Toshiba Semiconductor |
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TMP93CS32F 데이터시트(HTML) 156 Page - Toshiba Semiconductor |
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156 / 180 page  TMP93CS32 2004-02-10 93CS32-154 4.4 Serial Channel Timing (1) I/O interface mode 1. SCLK input mode Variable 12.5 MHz 20 MHz Parameter Symbol Min Max Min Max Min Max Unit SCLK cycle tSCY 16x 1.28 µs 0.8 µs ns Output data → Rising/falling edge of SCLK tOSS tSCY/2 − 5x − 50 190 100 ns SCLK rising/falling edge → Output data hold tOHS 5x − 100 300 150 ns SCLK rising/falling edge → Input data hold tHSR 0 0 0 ns SCLK rising/falling edge → Effective data input tSRD tSCY − 5x − 100 780 450 ns Note: SCLK rising/falling timing; SCLK rising in the rising mode of SCLK, SCLK falling in the falling mode of SCLK. 2. SCLK output mode Variable 12.5 MHz 20 MHz Parameter Symbol Min Max Min Max Min Max Unit SCLK cycle (programmable) tSCY 16x 8192x 1.28 µs 655.36 µs 0.8 µs 409.6 µs ns Output data → SCLK rising edge tOSS tSCY − 2x − 150 970 550 ns SCLK rising edge → Output data hold tOHS 2x − 80 80 20 ns SCLK rising edge → Input data hold tHSR 0 0 0 ns SCLK rising edge → Effective data input tSRD tSCY − 2x − 150 970 550 ns (2) UART mode (SCLK0 and SCLK1 are external input) Variable 12.5 MHz 20 MHz Parameter Symbol Min Max Min Max Min Max Unit SCLK cycle tSCY 4x + 20 340 220 ns SCLK low level pulse width tSCYL 2x + 5 165 105 ns SCLK high level pulse width tSCYH 2x + 5 165 105 ns 0 SCLK (Input falling edge mode) Output data TXD SCLK Output mode/ Input rising edge mode 123 3 2 1 0 tSCY tOSS tOHS tSRD tHSR Valid Valid Valid Valid Input data RXD |
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