TMP86CS49FG datasheet(219/252 Pages) TOSHIBA

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Page 205

TMP86CS49FG

16.6 Data Transfer of I2C Bus

16.6.1 Device initialization

For initialization of device, set the ACK in SBICRA to “1” and the BC to “000”. Specify the data length to 8

bits to count clocks for an acknowledge signal. Set a transfer frequency to the SCK in SBICRA.

Next, set the slave address to the SA in I2CAR and clear the ALS to “0” to set an addressing format.

After confirming that the serial bus interface pin is high level, for specifying the default setting to a slave

receiver mode, clear “0” to the MST, TRX and BB in SBICRB, set “1” to the PIN, “10” to the SBIM, and “00”

to bits SWRST1 and SWRST0.

Note:The initialization of a serial bus interface circuit must be complete within the time from all devices which are

connected to a bus have initialized to and device does not generate a start condition. If not, the data can not

be received correctly because the other device starts transferring before an end of the initialization of a serial

bus interface circuit.

16.6.2 Start condition and slave address generation

Confirm a bus free status (BB = 0).

Set the ACK to “1” and specify a slave address and a direction bit to be transmitted to the SBIDBR.

By writing “1” to the MST, TRX, BB and PIN, the start condition is generated on a bus and then, the slave

address and the direction bit which are set to the SBIDBR are output. The time from generating the START

condition until the falling SCL pin takes tLOW.

An INTSBI interrupt request occurs at the 9th falling edge of a SCL clock cycle, and the PIN is cleared to

“0”. The SCL pin is pulled-down to the low level while the PIN is “0”. When an interrupt request occurs, the

TRX changes by the hardware according to the direction bit only when an acknowledge signal is returned from

the slave device.

Note 1: Do not write a slave address to be output to the SBIDBR while data is transferred. If data is written to the

SBIDBR, data to been outputting may be destroyed.

Note 2: The bus free must be confirmed by software within 98.0

µs (The shortest transmitting time according to the

I2C bus standard) after setting of the slave address to be output. Only when the bus free is confirmed, set

"1" to the MST, TRX, BB, and PIN to generate the start conditions. If the writing of slave address and setting

of MST, TRX, BB and PIN doesn't finish within 98.0

µs, the other masters may start the transferring and the

slave address data written in SBIDBR may be broken.

Figure 16-9 Start Condition Generation and Slave Address Transfer

16.6.3 1-word data transfer

Check the MST by the INTSBI interrupt process after an 1-word data transfer is completed, and determine

whether the mode is a master or slave.

Start condition

Slave address + Direction bit

R/W

Acknowledge

signal from a

slave device

SCL pin

SDA pin

INTSBI

interrupt request

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