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TMC2192 데이터시트(PDF) 28 Page - Cadeka Microcircuits LLC. |
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TMC2192 데이터시트(HTML) 28 Page - Cadeka Microcircuits LLC. |
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28 / 69 page ![]() TMC2192 PRODUCT SPECIFICATION 28 REV. 1.0.0 8/13/03 Layering Engine Control Registers for this section The TMC2192 features a robust layering engine with three possible input layers controlled by two keying controls. The layer assignments are shown in Table 22, along with the key- ing control. The keying controls, KEY pin or OL4-0 are aligned with the incoming pixel data stream and are then delayed throughout the chip to be continuously aligned with the input video streams. A generic overview of the keying and layering features is shown in Figure 21. Figure 20. Layering Engine Overlay Mixer The OL[4:0] bus provides the ability to overlay 30 different 24 bit values onto the pixel data path. The 24 bit overlay col- ors must be the same format as the incoming Pixel data. For Y,Cb,Cr input formats the range of Y values spans the entire range of the format, 1 to 254, this enables super whites and super blacks in the overlay palette. When OL[4:0] is equal to 00h the pixel data port to be the output of the overlay mixer. If OL[4:0] is in the range of 1 to 31 then the output source is one of 30 possible overlay col- ors, see Table 22. Overlay Address Map. When OL4-0 equal to 16, the overlay mixer produces a pixel data output with half the luminance magnitude and chrominance magnitude. Any OL4-0 value greater than 16 will result in a overlay mix with a full amplitude overlay and the pixel data with half amplitude pixel data (PD) or half amplitude CVBS data as its values. This allows for transparent overlays or produce shadow boxes around overlaid text. The midpoint of the rising and falling edges on the mixed output is determined by the transition of the OL[4:0] pins in Address Bit(s) Name 0x04 2 SKEN 0x05 3-2 OMIX 0x07 6 SKFLIP 0x09 7 HKEN 0x09 6 BUKEN 0x09 5 SKEXT 0x09 4 DKDIS 0x09 3 EKDIS 0x09 2 FKDIS 0x09 1-0 LAYMODE 0x0A 7-0 DKEYMAX 0x0B 7-0 DKEYMIN 0x0C 7-0 EKEYMAX 0x0D 7-0 EKEYMIN 0x0E 7-0 FKEYMAX 0x0F 7-0 FKEYMIN Address Bit(s) Name Table 18. Layering and Keying Modes LAYMODE BACKGROUND MIDGROUND FOREGROUND Image Source Image Source Keying Control Image Source Keying Control 0 PD OVERLAY OL4-0 CVBS KEY or Data Key 1 PD CVBS KEY or Data Key OVERLAY OL4-0 2 CVBS OVERLAY OL4-0 PD KEY or Data Key 3 CVBS PD KEY or Data Key OVERLAY OL4-0 PD DATA KEY KEY OVERLAY MIXER OLUT OL4-0 KEYING MIXER CVBS PD YC dT dT dT dT dT dT dT COMP LOGIC LOGIC 1/2AMP 65-6294-23 |
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