TMC2192 datasheet(44/69 Pages) CADEKA

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TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

Control Register Deﬁnitions (continued)

DAC Control Register (0x11)

76543210

DRSSEL

RESERVED

COMP2DB

SINEN

REFSEL

LUMDIS

CHRMDIS

BURSTDIS

Reg

Bit

Name

Description

DRSSEL

DRS Selection.

When DRSSEL is HIGH, PD[7:0] is routed to the DRS detection block.

When DRSSEL is LOW, CVBS[9:2] is routed to the DRS detection block.

RESERVED

Program Low

COMP2DB.

Composite 2 Overflow Control.

When COMP2DB is HIGH, the digital range of the composite sumer is 0 to

2047 with half the digital resolution. When COMP2DB is LOW, the digital

output of the composite summer is 0 to 1023, all values exceeding 1023 or

below 0 are clipped.

SINEN

X/Sine(X) Filter Enable.

When SINEN is LOW, the X/Sin(X) filter is bypassed.

When SINEN is HIGH, the X/Sin(X) filter is used to compensate for the

DAC roll-off at high frequencies.

RESERVED

Program Low

LUMDIS

Luma Disable.

When LUMDIS is LOW, the luminance data on the composite data path is

enabled. When LUMDIS is HIGH, the luminance data on the composite

data path is disabled.

CHRMDIS

Chroma Disable.

When CHRMDIS is LOW, the chrominance data on the composite data

path is enabled. When CHRMDIS is HIGH, the chrominance data on the

composite data path is disabled.

BURSTDIS

Burst Disable.

When BURSTDIS is LOW, the burst is enabled.

When BURSTDIS is HIGH, the burst is disabled.

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