TMC2192 datasheet(30/69 Pages) CADEKA

30 / 69 page

TMC2192

PRODUCT SPECIFICATION

REV. 1.0.0 8/13/03

In read mode, the address is accompanied by a HIGH on the

R/W pin during a falling edge of CS. The data output pins go

to a low-impedance state tDOZ after CS falls. Valid data are

present on D7-0 tDOM after the falling edge of CS. Because

this port operates asynchronously with the pixel timing,

there is an uncertainty in this data valid output delay of one

PXCK period. This uncertainty does not apply to tDOZ.

Writing data to speciﬁc control registers of the TMC2192

requires that the 8 bit address of the control register of inter-

est be written prior to the data. This control register address

is the base address for subsequent write operations. The base

address auto increments by one for each byte of data written

after the data byte intended for the base address. If more

bytes are transferred than there are available addresses, the

address will not increment and remain at its maximum value

of 4Ch.

Writing data to speciﬁc OLUT location of the TMC2192

requires that the 8 bit address of the OLUT location of inter-

est be written prior to the data sequence. This OLUT loca-

tion address is the base address for subsequent write

operations. The base address auto increments by one for

each sequence of three (3) bytes of data written after the data

byte intended for the base address. The sequence of data

transfer is Y, Cb, Cr , after the Cr byte is transferred the base

address will increment by one (1).

Figure 23. Microprocessor Parallel Port – Write Timing

Figure 24. Microprocessor Parallel Port – Read Timing

Table 20. Parallel Port Control

A1-0

R/W

Action

Load D7-0 into Control Register

pointer (block 0)

Read Control Register pointer on

D7-0

Load D7-0 into addressed OLUT

Location pointer (block 0)

Read addressed OLUT Location

pointer on D7-0.

Write D7-0 to addressed Control

Read addressed Control Register

on D7-0

Write D7-0 to addressed OLUT

Location

Read addressed OLUT Location on

D7-0

tPWLCS

tSA

tSD

tHA

tHD

tPWHCS

65-6294-26

R/W

ADR

D7-0

tPWLCS

tSA

tDOM

tHA

tHOM

tDOZ

tPWHCS

R/W

ADR

D7-0

65-6294-27

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