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TMC2192 데이터시트(PDF) 4 Page - Cadeka Microcircuits LLC. |
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TMC2192 데이터시트(HTML) 4 Page - Cadeka Microcircuits LLC. |
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4 / 69 page ![]() TMC2192 PRODUCT SPECIFICATION 4 REV. 1.0.0 8/13/03 Pin Assignments Pin Definitions Pin Name Pin Number Value Description CLOCK, SYNC, & CONTROL INPUTS (6 pins) DCVEN 57 TTL Digital CVBS Output Enable. When DCVEN is LOW, the Comp2 output prior to the D/A is routed to D7-0, FLD2-1 providing a digital composite output. When DCVEN is HIGH, D7-0 and FLD2-1 operate in their normal mode. HSIN 56 TTL Horizontal Sync Input. When operating in slave, Genlock, or DRS-Lock the TMC2192 will start a new horizontal line with each falling edge of HSIN. KEY 20 TTL Hard Key selection. When the control register bit HKEN is set HIGH and the hardware KEY pin is high, the video data considered to be the foreground. is routed to the COMP2 output. This control signal is data aligned so that the pixel that is present on the PD port when KEY signal is latched is at the midpoint of the key transition. When HKEN is LOW, Key is ignored. PD1 PD0 DGND VDD VSIN HSIN DCVEN SER CS\/SCL R/W\/SDA A1/SA1 A0/SA0 D7 D6 D5 D4 D3 D2 D1 D0 DGND VDD PDC HSOUT VSOUT LINE4 LINE3 LINE2 LINE1 LINE0 VDDA COMP CBYPCOMP AGND CHROMA CBYPCHROM VDDA RREFCHROM AGND LUMA CBYPLUMA VDDA RREFLUMA AGND AGND VDDA VDDA AGND AGND KEY OL4 OL3 OL2 OL1 OL0 DGND PD23 PD22 PD21 PD20 1 30 31 50 65-6294-14 100 81 80 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function 51 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Function PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 VDD DGND PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function FLD2 FLD1 FLD0 CVBS9 CVBS8 CVBS7 CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1 CVBS0 RESET PXCK VDD DGND VREF RREFCOMP AGND |
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