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TMC2192 데이터시트(PDF) 34 Page - Cadeka Microcircuits LLC. |
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TMC2192 데이터시트(HTML) 34 Page - Cadeka Microcircuits LLC. |
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34 / 69 page ![]() TMC2192 PRODUCT SPECIFICATION 34 REV. 1.0.0 8/13/03 VBI Ped Enable Registers 14 7-0 VBIPEDEM VBI Pedestal Enable, Even Fields 15 7-0 VBIPEDEL VBI Pedestal Enable, Even Fields 16 7-0 VBIPEDOM VBI Pedestal Enable, Odd Fields 17 7-1 VBIPEDOL VBI Pedestal Enable, Odd Fields 17 0 HVA Horizontal and Vertical Sync Alignment Vertical Blanking Interval Enable Registers 18 7 Reserved Program Low 18 6 GLKCTL1 Genlock Control Register 1 18 5 GLKCTL0 Genlock Control Register 0 18 4-0 VBIENF1 VBI Active Video Enable, Field 1 19 7 SHORT Test Register 19 6 T512 EH/SL Offset Control Bit 19 5 HALFEN Half Line Enable 19 4-0 VBIENF2 VBI Active Video Enable, Field 2 Pedestal Height Register 1A 7 Reserved Program Low 1A 6-0 PEDHGT1 Composite Pedestal Height Closed Caption Registers 1C 7-0 CCD1 First Byte of CC Data 1D 7-0 CCD2 Second Byte of CC Data 1E 7 CCON Enable CC Data Packet 1E 6 CCRTS Request to Send Data 1E 5 CCPAR Auto Parity Generation 1E 4 CCFLD CC Field Select 1E 3-0 CCLINE CC Line Select Timing Registers 1F 7-0 PDCNT Pixel Data Control Start 20 7-0 SY Horizontal Sync Tip Duration 21 7-0 BR Breezeway Duration 22 7-0 BU Burst Duration 23 7-0 CBP Color Back Porch Duration Table 22. Control Register Map (continued) Reg Bit Mnemonic Function 24 7-0 XBP Extended Color Back Porch Duration 25 7-0 VA Active Video Region Duration 26 7-0 VC Active Video Region 2nd Half Line Duration 27 7-0 VB Active Video Region 1st Half Line Duration 28 7-0 EL Equalization Pulse Low Duration 29 7-0 EH Equalization Pulse High Duration 2A 7-0 SL Vertical Sync Pulse Low Duration 2B 7-0 SH Vertical Sync Pulse High Duration 2C 7-0 FP Front Proch Duration 2D 7-6 XBP Extended Color Back Porch Duration 2D 5-4 VA Active Video Duration 2D 3-2 VB Active Video Region 1st Half Line Duration 2D 1-0 VC Active Video Region 2nd Half Line Duration 2E 7-5 FIELD Field Identification (read only) 2E 4-0 LTYPE Line Type Identification (read only) 2F 7-0 CBL Color Bar Duration Color Space Matrix Registers 30 7-0 MCF1L Matrix Coefficient #1 31 7-0 Reserved Program Low 32 7-0 Reserved Program Low 33 7-0 MCF2L Matrix Coefficient #2 34 7-0 Reserved Program Low 35 7-0 MCF3L Matrix Coefficient #3 36 7-0 Reserved Program Low 37 7-0 Reserved Program Low Table 22. Control Register Map (continued) Reg Bit Mnemonic Function |
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